The present invention relates to arrangements and methods for aligning a semiconductor transducer element, formed on a semiconductor chip or die, to a signal conveying element. An important category of the present invention relates to arrangements and methods for aligning an optical fiber to an optoelectronic device, such as a laser or photodetector formed on a semiconductor chip.
Conventionally, a significant part of the cost of an optoelectronic package lies in the equipment and procedures employed to align an optical fiber to an optically active optoelectronic chip (such as a laser or photodetector). Since large numbers of these devices are manufactured yearly, efforts are constantly being made to reduce this cost.
In xe2x80x9cLow-Cost Fabrication of Optical Subassemblies (M. S. Cohen et al., Proc. 46th ECTC, pp. 1093-1100, 1996), there is disclosed a method of active alignment with powered-on devices in which special equipment is required and a lengthy sequential process is employed (i.e., one fiber aligned to one chip at a time): While the optoelectronic chip described in this reference is housed in an hermetically sealed metal and glass xe2x80x9cTO canxe2x80x9d enclosure, in principle the same method could also be used for a non-hermetically sealed chip.
In xe2x80x9cGigabit transmitter array modules on silicon waferboardxe2x80x9d (A. Armiento et al., Proc. FEEE Trans. Comp. Hybrids and Manufacturing, vol. 15, pp. 1072-1080, 1992), there is disclosed a passive alignment technique using special mechanical locating features on the optoelectronic chip and the substrate wherein the chip is mechanically keyed to the substrate. This technique requires special processing of both the chip and the substrate. Here, the chip is not housed in a TO can.
In xe2x80x9cFlip-chip equipment for high-end electro-optical modulesxe2x80x9d (K. S. Cooper et al., Proc. 48th ECTC, pp. 176-180, 1998), there is disclosed a method of passive alignment using expensive special purpose and precision tooling, which also involves sequential processing. The alignment is carried out by matching fiducial marks on the chip and on the substrate. Here, the chip is not housed in a TO can.
All of the conventional methods described above are expensive to realize and thus add substantial cost to the package.
The general concept of using lithographic processing to create an on-chip fiber-guiding structure that enables alignment of a fiber to an optoelectronic device has been contemplated previously. As previously contemplated, such a concept offered a way of overcoming the difficulties associated with the types of conventional alignment methods described above. Particularly, in 1970, this concept was utilized to align a fiber to an LED (C. A. Burns and R W. Dawson, xe2x80x9cSmall-area high-current-density GaAs electroluminescent diodes and a method of operation for improved degradation characteristicsxe2x80x9d, Appl. Phys. Lett., vol. 17, pp. 97-99, 1970). However, the fiber-aligning structure in question is a wet-etched well fabricated directly in the gallium arsenide (GaAs) substrate, which does not offer highly accurate fiber alignment because of the hemispherical shape of the well. In addition to many difficulties in controlling the etching process, the etching process itself results in a mechanical weakening of the fiber-aligning structure. Accordingly, a need has been recognized in connection with improving upon the deficiencies presented by this particular arrangement.
In accordance with at least one presently preferred embodiment of the present invention, fiber-to-chip alignment is achieved by employing lithographic tooling and processes which are commonly used in the semiconductor industry. Many of the processing steps are carried out in parallel on a wafer scale. The result is a significant cost savings in comparison with conventional arrangements such as those described heretofore.
The cost savings are achieved, at least in part, by way of the wafer-scale fabrication of fiber-guide structures directly on the optoelectronic device chips, lithographically, using standard semiconductor lithographic techniques. Each fiber-guide structure serves to guide a fiber into alignment with the optically active region of the chip. Since the fiber guides are lithographically patterned, excellent alignment with the optically active regions is assured. The present invention in accordance with at least one presently preferred embodiment, thus provides an inexpensive method of enabling passive alignment by use of standard lithographic tools instead of using any of the expensive procedures described above. After dicing the chips from the wafer, it is necessary only to insert the fibers into the fiber guides with the aid of simple fiber-handling tooling, and then to fix the fibers in place with a suitable adhesive.
Butt coupling from chip to fiber is one preferred manner of coupling the chips to the fibers; it avoids the use, and cost, of additional optical elements. Sufficiently high coupling efficiencies are achieved by maintaining short fiber-to-chip distances to reduce the extent to which a diverging optical beam expands before striking a receiving optical component.
Compared to the previously cited on-chip fiber-guiding structures that enable the alignment of a fiber to an optoelectronic device, the present invention offers very straight vertical walls by way of a straightforward, standard lithographic process, avoids the necessity of a chemical etch process directly in the semiconductor material, and provides precise alignment of the fiber to the optically active chip.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings. The scope of the invention will be expressed in the appended claims.